1. Technical Field
The invention relates generally to integrated circuit (IC) chip fabrication, and more particularly, to a copper contact via structure using a hybrid barrier layer.
2. Background Art
In current complementary metal-oxide semiconductor (CMOS) technology, the middle-of-the-line (MOL) contact between a silicide source/drain region of a field effect transistor (FET) and the first back-end-of-line (BEOL) metal layer is made with a tungsten (W) plug using a titanium-titanium nitride (Ti/TiN) barrier layer. MOL indicates a layer of interconnects from a transistor level to other layers that scale the wiring upwardly, which is the BEOL layers. As the size of the MOL contact scales to smaller sizes, such as 65 nm and beyond, the resistance of the tungsten (W) plug becomes a significant limitation of device and circuit performance. To reduce this contact resistance, the tungsten (W) plug must be replaced by a lower resistance material such as copper (Cu). One problem preventing copper (Cu) from being integrated into the MOL contact plug is copper (Cu) proximity to the device and diffusion into the silicon. While physical vapor deposition (PVD) of the TaN/Ta barrier layer processes have been proven as effective diffusion barriers for copper (Cu) in BEOL metal and via levels, they cannot be directly copied into the MOL contact process flow because PVD TaN/Ta films have poor conformality. In addition, the BEOL barrier layer process typically uses a sputter etch to redistribute the material to obtain good sidewall coverage in the vias and little to no coverage at the bottom of the via to facilitate a good copper-to-copper electrical contact. As a result, in the case of a MOL copper contact process, the BEOL process would be insufficient as a diffusion barrier at the bottom of the via because there is no barrier layer created.